The source-synchronous bus has been used to increase the speed of buses in many designs. Data and clock are sourced from the same device on the bus. The receiving device uses the clock from the bus to sample the data on the bus. Since the clock and data are driven and distributed similarly, they have similar delays and hence such buses can be run faster than buses using other clocking schemes.
At higher speed, being able to drive a clock becomes challenging especially when the data pins are driven and sampled on both edges of the clock. This is referred to as double-data rate or DDR.
One of the limitations on speed derives from the fact that as the number of data pins gets large, the skew between those pins increases, where Clock Skew is the variation in the transition point of a clock signal due to delay in the propagation path. Since all pins need to be sampled with the same clock, clock skew limits the speed of the bus. In DDR3, SRAMs, and in fast packet forwarding ASICs, this limitation is overcome by limiting the number of data pins associated with a clock pin. For wider data buses, multiple copies of source-synchronous clocks are used. But still the skew between copies of clocks has to be limited to much less than the clock period in order to align the data sampled with different copies of clocks.
Accordingly, new parallel interfaces need to be developed that allow high speed data transfer between Devices with a large number of pins.